When an address or data byte has been transmitted onto the bus then this must be ACKNOWLEDGED by the slave(s). In case of an address: If the address matches its own then that slave and only that slave will respond to the address with an ACK. In case of a byte transmitted to an already addressed slave then that slave will respond with an ACK as well.
The slave that is going to give an ACK pulls the SDA line low immediately after reception of the 8th bit transmitted, or, in case of an address byte, immediately after evaluation of its address. In practical applications this will not be noticeable.
This means that as soon as the master pulls SCL low to complete the transmission of the bit (1), SDA will be pulled low by the slave (2).
The master now issues a clock pulse on the SCL line (3). the slave will release the SDA line upon completion of this clock pulse (4).
The bus is now available again for the master to continue sending data or to generate a stop condition.
In case of data being written to a slave, this cycle must be completed before a stop condition can be generated. The slave will be blocking the bus (SDA kept low by slave) until the master has generated a clock pulse on the SCL line.
Upon reception of a byte from a slave, the master must acknowledge this to the slave device. The master is in full control of the SDA and the SCL line. After transmission of the last bit to the master (1) the slave will release the SDA line.
The SDA line should then go high (2). The Master will now pull the SDA line low (3) .
Next, the master will put a clock pulse on the SCL line (4). After completion of this clock pulse, the master will again release the SDA line (5). The slave will now regain control of the SDA line (6). Note: The above waveform is slightly exaggerated. You will not notice SDA going high in (2) and (5). A small spike might barely be visible. Note: An Acknowledge of a byte received from a slave is always necessary, EXCEPT on the last byte received.
If the master wants to stop receiving data from the slave, it must be able to send a stop condition.
Since the slave regains control of the SDA line after the ACK cycle issued by the master, this could lead to problems.
Let's assume the next bit ready to be sent to the master is a 0. The SDA line would be pulled low by the slave immediately after the master takes the SCL line low. The master now attempts to generate a Stop condition on the bus. It releases the SCL line first and then tries to release the SDA line - which is held low by the slave. Conclusion: No Stop condition has been generated on the bus.
This condition is called a NACK : Not ACKnowledge . Do not confuse this with No ACKnowledge:Condition Can Only Occur...
Not acknowledge (NACK) After a master has read a byte from a slave
No acknowledge After a master has written a byte to a slave
This is not exactly a condition. It is merely a state in the data flow between master and slave.
If, after transmission of the 8th bit from the master to the slave the slave does not pull the SDA line low, then this is considered a No ACK condition.
This means that either :
The slave is not there (in case of an address)
The slave missed a pulse and got out of sync with the SCL line of the master.
The bus is "stuck". One of the lines could be held low permanently.
In any case the master should abort by attempting to send a stop condition on the bus.
A test for a "stuck bus" can be performed in the stop condition cycle.