Special adresses

In the I2C address map there are so-called "reserved addresses". This section contains some more details on these addresses and what they do. For information about the  Extended Addressing Mode, please refer to the corresponding chapter.


Note 1: The general call address

This address is being used to access all devices on the bus which are capable of handling the general call and need this data. Devices which are capable of handling this general call but do not need it will not answer.

All bytes transferred after this address may or may not be taken in by the slaves that are responding to it. If no slave is acknowledging a transmitted byte, the operation is stopped by issuing a STOP on the bus.

The meaning of the general call address is specified in the 1st byte transmitted after this "general call". This first byte can contain the following information:

If the LSB is set to 0:0000-0110 Reset and write programmable part of slave address. All devices who respond to this will reset and take in the programmable part of their address. This is done by re-reading the levels on the address select pins of the device (if any). This command can be used to reset an entire I2C system.

0000-0100 The same as above but without the reset . This can be useful if the state of the address select pins of a device are configurable. This way the device address will change.

If the LSB is set to 1:xxxx-xxx1 This is a Hardware Call. If a device needs urgent attention from a master device without knowing which master it needs to turn to, it can use this call. This is a call "to whom it may concern". The device then embeds its own address into the message. This call means as much as: Please contact me, I need to be serviced. All masters will listen and the master that knows how to handle the device with the address transmitted will contact its slave and act appropriately.

Note 2: The START address

This can be used between masters. A master which does not have an I2C interface in hardware but in software needs to monitor the bus all the time. Since this can require a lot of processing time, the START address was introduced. The masters can sample the bus at a low rate. As soon as they detect that the SDA line is low (it is held low for over 7 clock periods) it can switch to a higher sampling rate to detect the Start condition.

This address is not followed by a stop condition but rather by a repeated start condition.

Notes 3 and 4: These addresses are used when data other than I2C data has to be transmitted over the bus.

Note 5: These addresses are for further expansion and are currently not allowed.

Note 6: This will be discussed in detail in the section about 10-bit addressing.
A Stop condition ALWAYS denotes the END of a transmission. Even if it is issued in the middle of a transaction or in the middle of a byte. It is "good behaviour" for a chip that, in this case, it disregards the information sent and resumes the "listening state", waiting for a new start condition.
    
In total, this sequence has to be performed 8 times to complete the data byte. Bytes are always transmitted MSB first.

The meaning of all bytes being read depends on the slave. There is no such thing as a "universal status register". You need to consult the data sheet of the slave being addressed to know the meaning of each bit in any byte transmitted.


Extended Adressing

Due to the increasing popularity of the I2C bus the 7-bit address space got exhausted. This started posing problems for people currently in the phase of designing a new I2C compatible IC. Therefore the I2C standard has been updated to implement a 10-bit addressing mode.

A chip that conforms to the new standard receives two address bytes. The first consists of the extended addressing reserved address including the 2 MSB's of the device address and the Read/Write bit. The second byte contains the 8 LSB's of the address.

This scheme insures that the 10 bit addressing mode stays completely transparent for the other devices on the bus. Any new design should implement this new addressing scheme.

© Vincent Himpe 2016